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integrated circuit systems, inc. ICS9248-195 0375d?02/02/04 block diagram frequency generator & integrated buffers for pentium ii / iii tm & k6 pin configuration 48-pin ssop and tssop * internal pull-up resistor of 120k to vdd vddref *spread/ref0 gndref x1 x2 vddpci *cpu2.5_3.3#/pciclk_f *fs3/pciclk0 gndpci *sel24_48#/pciclk1 *selpcie_6#/pciclk2 pciclk3 pciclk4 vddpci buffer in gndpci pciclk5 pciclk6/ vddcor pci_stop# *vtt_pwrgd/pd# gnd48 s data sclk pciclk_e ref1/fs2* vddlcpu cpuclk_f cpuclk0 gndlcpu cpuclk1 cpuclk2 clk_stop# gndsdr sdram_f sdram0 sdram1 vddsdr sdram2 sdram3 gndsdr sdram4 sdram5 vddsdr sdram6 sdram7 vdd48 48mhz/fs0* 24_48mhz/fs1* ICS9248-195 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 recommended application: 440bx, mx, via pm/pl/ple 133 style chip set, with coppermine or tualatin processor, for note book applications. output features: 4 - cpus @ 2.5v/3.3v including 1 free running cpuclk_f 9 - sdram @ 3.3v 7 - pci @ 3.3v, including 1 free running pciclk_f 1 - pci early @ 3.3v 1 - 48mhz, @ 3.3v fixed. 1 - 24/48mhz @ 3.3v 2 - ref @3.3v, 14.318mhz. features: up to 137mhz frequency support 97mhz to support high-end amd processor. support power management: clk, pci, stop and power down mode from i 2 c programming. spread spectrum for emi control uses external 14.318mhz crystal fs pins for frequency select functionality 2 t i b6 t i b5 t i b4 t i bk l c u p ck l c i c p 0000 7 6 . 6 63 3 . 3 3 000 1 0 0 . 0 0 13 3 . 3 3 00 10 7 6 . 6 63 3 . 3 3 00 11 3 3 . 3 3 13 3 . 3 3 0100 7 6 . 6 63 3 . 3 3 0101 0 0 . 0 0 13 3 . 3 3 0110 0 0 . 0 0 13 3 . 3 3 0 111 3 3 . 3 3 13 3 . 3 3 1000 7 6 . 6 63 3 . 3 3 10 0 1 0 0 . 0 0 13 3 . 3 3 10 10 0 0 . 0 90 0 . 0 3 10 1 1 3 3 . 3 3 13 3 . 3 3 1100 0 0 . 0 70 0 . 5 3 110 1 0 0 . 5 0 10 0 . 5 3 1110 3 3 . 3 3 13 3 . 3 3 1111 0 0 . 0 4 10 0 . 5 3 key specifications: cpu output jitter @ 2.5v: <300ps cpu output jitter @ 3.3v: <250ps pci output jitter @ 3.3v: <250ps cpu output skew @ 2.5v: <175ps cpu output skew @ 3.3v: <175ps pci output skew @ 3.3v: <500ps pci early to pci skew @ 3.3v: typ = 3ns sdram output skew @ 3.3v: <500ps
2 ICS9248-195 0375d?02/02/04 pin descriptions notes: 1: internal pull-up resistor of 120k to 3.3v on indicated inputs 2: bidirectional input/output pins, input logic levels are latched at internal power-on-reset. use 10kohm resistor to program logic hi to vdd or gnd for logic low. n i p r e b m u n e m a n n i pe p y tn o i t p i r c s e d 1f e r d d vr w pv 3 . 3 l a n i m o n , y l p p u s r e w o p l a t x , f e r 2 d a e r p s 2 , 1 n i " n o " s i g n i d a e r p s , " h g i h " s i t l u a f e d p u - r e w o p . t u p n i e l b a n e m u r t c e p s d a e r p s h g i h e v i t c a 0 f e rt u o s d a o l s u b a s i r o f r e f f u b r e g n o r t s e h t s i t u p t u o f e r s i h t . k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 0 2# p o t s _ i c pn i ) 0 = e d o m , e d o m e l i b o m n i ( w o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c k l c i c p s t l a h , 6 1 , 9 , 3 4 4 , 0 4 , 3 3 d n gr w pd n u o r g 41 xn i k c a b d e e f d n a ) f p 6 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 52 xt u o. z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c 4 1 , 6i c p d d vr w pv 3 . 3 l a n i m o n k l c i c p d n a f _ k l c i c p r o f y l p p u s 7 # 3 . 3 _ 5 . 2 u p c 2 , 1 n i . t u p n i d e h c t a l . u p c v 3 . 3 = w o l , u p c v 5 . 2 = h g i h . v 3 . 3 r o 5 . 2 s i u p c l d d v r e h t e h w s e t a c i d n i f _ k l c i c pt u o . t n e m e g a n a m r e w o p r o f # p o t s _ i c p y b d e t c e f f a t o n k c o l c i c p g n i n n u r e e r f 8 3 s f 2 , 1 n i. t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 0 k l c i c pt u o ) y l r a e u p c ( w e k s s n 4 - 1 h t i w s k c o l c u p c o t s u o n o r h c n y s . t u p t u o k c o l c i c p 0 1 # 8 4 _ 4 2 l e s 2 , 1 n iz h m 8 4 = w o l n e h w z h m 8 4 r o 4 2 r e h t i e s t c e l e s 1 k l c i c pt u o ) y l r a e u p c ( w e k s s n 4 - 1 h t i w s k c o l c u p c o t s u o n o r h c n y s . t u p t u o k c o l c i c p 1 1 # 6 _ e i c p l e s 2 , 1 n i ) . k l c i c p y l r a e " h g i h " s i t l u a f e d p u - r e w o p 8 1 n i p r o f ( . t u p n i h c t a l t c e l e s i c p l a m r o n r o y l r a e i c p 2 k l c i c pt u o. t u p t u o k c o l c k l c i c p 2 1 , 3 1 , 7 1) 3 : 5 ( k l c i c pt u o ) y l r a e u p c ( w e k s s n 4 - 1 h t i w s k c o l c u p c o t s u o n o r h c n y s . s t u p t u o k c o l c i c p 5 1n i r e f f u bn i. s t u p t u o m a r d s r o f s r e f f u b t u o n a f o t t u p n i 8 1 - _ k l c i c p / 6 k l c i c p e t u o # 6 _ e i c p l e s y b e l b a t c e l e s t u p t u o k c o l c i c p y l r a e r o t u p t u o k c o l c i c p 9 1r o c d d vr w pv 3 . 3 . e r o c l l p e h t r o f n i p r e w o p 1 2 d n g r w p _ t t vn i d g r w p _ t t v n e h w . l a n g i s # d p d n a d g r w p _ t t v r o f n i p t u p n i n o i t c n u f l a u d a s a s t c a n i p s i h t n a s i n i p e h t r e t f a e r e h t n o r e w o p t a d e h c t a l e b l l i w t c e l e s y c n e u q e r f e h t h g i h s e o g . n i p n w o d r e w o p w o l e v i t c a s u o n o r h c n y s a # d p 1 n i e h t . e t a t s r e w o p w o l a o t n i e c i v e d e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a e h t f o y c n e t a l e h t . d e p p o t s e r a l a t s y r c e h t d n a o c v e h t d n a d e l b a s i d e r a s k c o l c l a n r e t n i . s m 4 n a h t r e t a e r g e b t o n l l i w n w o d r e w o p 2 28 4 d n gr w p. e r o c l l p d e x i f & s r e f f u b t u p t u o z h m 8 4 & 4 2 e h t r o f n i p d n u o r g , 2 3 , 1 3 , 9 2 , 8 2 8 3 , 7 3 , 5 3 , 4 3 ) 0 : 7 ( m a r d st u o . ) t e s p i h c y b d e l l o r t n o c ( n i p n i r e f f u b m o r f s t u p t u o r e f f u b t u o n a f , s t u p t u o k c o l c m a r d s 6 3 , 0 3r d s d d vr w p. v 3 . 3 l a n i m o n , e r o c l l p u p c d n a m a r d s r o f y l p p u s 3 2a t a d sn ii r o f t u p n i a t a d 2 t u p n i t n a r e l o t v 5 , t u p n i l a i r e s c 4 2k l c sn ii f o t u p n i k c o l c 2 t u p n i t n a r e l o t v 5 , t u p n i c 5 2 z h m 8 4 _ 4 2t u o0 1 n i p y b e l b a t c e l e s k c o l c t u p t u o z h m 8 4 r o z h m 4 2 1 s f 2 , 1 n i. t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 6 2 z h m 8 4t u ok c o l c t u p t u o z h m 8 4 0 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 7 28 4 d d vr w p. e r o c l l p d e x i f d n a s r e f f u b t u p t u o z h m 8 4 & 4 2 r o f r e w o p 9 3f _ m a r d st u o# p o t s _ u p c y b d e t c e f f a t o n . t u p t u o k c o l c m a r d s g n i n n u r e e r f 1 4# p o t s _ k l cn i . w o l n e v i r d n e h w l e v e l " 0 " c i g o l t a m a r d s & , k l c u p c s t l a h t u p n i s u o n o r h c n y s a s i h t 5 4 , 3 4 , 2 4) 0 : 2 ( k l c u p ct u ou p c l d d v y b d e r e w o p , s t u p t u o k c o l c u p c 6 4f _ k l c u p ct u o# p o t s _ u p c e h t y b d e t c e f f a t o n . k c o l c u p c g n i n n u r e e r f 7 4u p c l d d vr w pv 5 . 2 s k c o l c u p c r o f y l p p u s 8 4 1 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 2 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f
3 ICS9248-195 0375d?02/02/04 byte0: functionality and frequency select register (default = 0) serial configuration command bitmap notes: 1, default at power-up will be for latched logic inputs to define frequency. bit [2, 6:4] are default to 0011. 2, pwd = power-up default the ICS9248-195 is the single chip clock solution for notebook designs using the 440bx, mx, via pm/pl/ple 133 style chip set, with coppermine or tualatin processor, for note book applications. it provides all necessary clock signals for such a system. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9248- 195 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. general description bit pwd fs3 bit2 fs2 bit6 fs1 bit5 fs0 bit4 cpuclk pciclk center spread % down spread% 0 0 0 0 66.67 33.33 0.35% -0.70% 0 0 0 1 100.00 33.33 0.35% -0.70% 0 0 1 0 66.67 33.33 0.60% -1.20% 0 0 1 1 133.33 33.33 0.35% -0.70% 0 1 0 0 66.67 33.33 0.23% -0.45% 0 1 0 1 100.00 33.33 0.23% -0.45% 0 1 1 0 100.00 33.33 0.60% -1.20% 0 1 1 1 133.33 33.33 0.23% -0.45% 1 0 0 0 66.67 33.33 0.45% -0.90% 1 0 0 1 100.00 33.33 0.45% -0.90% 1 0 1 0 90.00 30.00 0.35% -0.70% 1 0 1 1 133.33 33.33 0.45% -0.90% 1 1 0 0 70.00 35.00 0.35% -0.70% 1 1 0 1 105.00 35.00 0.35% -0.70% 1 1 1 0 133.33 33.33 0.60% -1.20% 1 1 1 1 140.00 35.00 0.35% -0.70% 0 - normal note1 0011 description 1 0 1 0 = center spread spectrum modulation 1 = down spread spectrum modulation 0 - frequenc y is selected b y hardware select pins. latched inputs. 1 - frequency is controlled by i 2 c programming. 0 - runnin g 1 - tristate all outputs 0 1 - spread spectrum enabled bit 0 bit 7 bit 3 bit 2, 6:4 bit 1
4 ICS9248-195 0375d?02/02/04 notes: 1. inactive means outputs are held low and are disabled from switching. 2. latched register values will be inverted from pin values. default latch condition is for all latched inputs to be floating (pulled up via internal resistor) at power-up. byte 2: active/inactive register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b71 ) s i d / n e ( f _ k l c i c p 6 t i b8 11 ) s i d / n e ( 6 k l c i c p 5 t i b7 11 ) s i d / n e ( 5 k l c i c p 4 t i b3 11 ) s i d / n e ( 4 k l c i c p 3 t i b2 11 ) s i d / n e ( 3 k l c i c p 2 t i b1 11 ) s i d / n e ( 2 k l c i c p 1 t i b0 11 ) s i d / n e ( 1 k l c i c p 0 t i b81 ) s i d / n e ( 0 k l c i c p byte 1: active/inactive register (1 = enable, 0 = disable) byte 3: active/inactive register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b6 41 ) s i d / n e ( f _ k l c u p c 5 t i b-0 ) d e v r e s e r ( 4 t i b-0 ) d e v r e s e r ( 3 t i b9 31 ) s i d / n e ( f _ m a r d s 2 t i b2 41 ) s i d / n e ( 2 k l c u p c 1 t i b3 41 ) s i d / n e ( 1 k l c u p c 0 t i b5 41 ) s i d / n e ( 0 k l c u p c t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-0 ) d e v r e s e r ( 5 t i b-0 ) d e v r e s e r ( 4 t i b-0 ) d e v r e s e r ( 3 t i b8 21 ) s i d / n e ( 7 m a r d s 2 t i b9 21 ) s i d / n e ( 6 m a r d s 1 t i b1 31 ) s i d / n e ( 5 m a r d s 0 t i b2 31 ) s i d / n e ( 4 m a r d s
5 ICS9248-195 0375d?02/02/04 byte 4: active/inactive register (1 = enable, 0 = disable) byte 5: active/inactive register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. 2. latched register values will be inverted from pin values. default latch condition is for all latched inputs to be floating (pulled up via internal resistor) at power-up. t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-0 ) d e v r e s e r ( 5 t i b-0 # ) 8 4 _ 4 2 l e s ( 4 t i b-0 # 0 s f d e h c t a l 3 t i b-0 # 1 s f d e h c t a l 2 t i b-0 # 2 s f d e h c t a l 1 t i b-0 # 3 s f d e h c t a l 0 t i b-1 ) d e v r e s e r ( t i b# n i pd w pn o i t p i r c s e d 7 t i b4 31 ) s i d / n e ( 3 m a r d s 6 t i b5 31 ) s i d / n e ( 2 m a r d s 5 t i b7 31 ) s i d / n e ( 1 m a r d s 4 t i b8 31 ) s i d / n e ( 0 m a r d s 3 t i b6 21 ) s i d / n e ( z h m 8 4 2 t i b5 21 ) s i d / n e ( z h m 4 2 1 t i b8 41 ) s i d / n e ( 1 f e r 0 t i b21 ) s i d / n e ( 0 f e r
6 ICS9248-195 0375d?02/02/04 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v c l = 0 pf; select @ 66mhz 150 c l = 0 pf; select @ 100mhz 170 c l = 0 pf; select @ 133mhz 180 powerdown current i ddpd cl = 0 pf; input address vdd or gnd 600 a input frequency f i v d d = 3.3 v 14.32 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 45 pf clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 5.5 ms skew 1 t cpu-pci1 v t = 1.5 v 14ns 1 guaranteed by design, not 100% tested in production. ma operating supply current i dd3.3op electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units c l = 0 pf; select @ 66.8 mhz 15 c l = 0 pf; select @ 100 mhz 18 c l = 0 pf; select @ 133 mhz 25 powerdown current i ddlp d cl = 0 pf; input address vdd or gnd 10 ma skew 1 t cpu-pci 2 v t = 1.5 v; v tl = 1.25 v 14ns 1 guaranteed by design, not 100% tested in production. i ddl2.5 o perating supplycurren t ma
7 ICS9248-195 0375d?02/02/04 electrical characteristics - cpu t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20 pf parameter symbol conditions min typ max units output high voltage v oh2a i oh = -20 ma 2.4 v output low voltage v ol2a i ol = 12 ma 0.4 v output high current i oh2a v oh = 2.0 v -27 ma output low current i ol2a v ol = 0.8 v 22 ma rise time 1 t r2a v ol = 0.4 v, v oh = 2.4 v 1.35 2 ns fall time 1 t f2a v oh = 2.4 v, v ol = 0.4 v 1.44 2 ns duty cycle 1 d t2a v t = 1.5 v 45 50.3 55 % skew window 1 t sk2a v t = 1.5 v 70 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc2a v t = 1.5 v 160 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - cpu t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 20 pf parameter symbol conditions min typ max units output high voltage v oh2b i oh = -12 ma 2 v output low voltage v ol2b i ol = 12 ma 0.4 v output high current i oh2b v oh = 1.7 v -21 ma output low current i ol2b v ol = 0.7 v 22 ma rise time 1 t r2b v ol = 0.4 v, v oh = 2.0 v 1.40 1.8 ns fall time 1 t f2b v oh = 2.0 v, v ol = 0.4 v 1.70 1.8 ns v t = 1.25 v, < 133 mhz 45 52 55 v t = 1.25 v, >= 133 mhz 42 51 52 skew window 1 t sk2b v t = 1.25 v 60 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc2b v t = 1.25 v 143 250 ps 1 guaranteed by design, not 100% tested in production. % d t2b duty cycle 1
8 ICS9248-195 0375d?02/02/04 electrical characteristics - sdram t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 30 pf parameter symbol conditions min typ max units output high voltage v oh3 i oh = -28 ma 2.4 v output low voltage v ol3 i ol = 19 ma 0.4 v output high current i oh3 v oh = 2.0 v -46 ma output low current i ol3 v ol = 0.8 v 32 ma rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 1.17 1.6 ns fall time 1 t f3 v oh = 2.4 v, v ol = 0.4 v 1.20 1.6 ns dut y c y cle 1 d t3 v t = 1.5 v 42 50 52 % skew window 1 t sk3 v t = 1.5 v 210 250 ps propagation time 1 (buffer in to output) t sk3 v t = 1.5 v 4.10 5 ns 1 guaranteed by design, not 100% tested in production. electrical characteristics - pci t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 30 pf parameter symbol conditions min typ max units output high voltage v oh1 i oh = -18 ma 2.4 v output low voltage v ol1 i ol = 9.4 ma 0.4 v output high current i oh1 v oh = 2.0 v -33 ma output low current i ol1 v ol = 0.8 v 38 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.60 2.2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.50 2.2 ns duty cycle 1 d t1 v t = 1.5 v 45 51.5 55 % skew window 1 t sk1 v t = 1.5 v 380 500 ps skew window 1 t sk2 v t = 1.5 v pciclke to pci [5:0] 2 2.71 4 ns jitter, absolute 1 t jabs1 v t = 1.5 v 120 250 ps 1 guaranteed by design, not 100% tested in production.
9 ICS9248-195 0375d?02/02/04 electrical characteristics - 24,48mhz t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -14 ma 2.4 v output low voltage v ol5 i ol = 6 ma 0.4 v output high current i oh5 v oh = 2.0 v -20 ma output low current i ol5 v ol = 0.8 v 16 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.93 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 2.63 4 ns duty cycle 1 d t5 v t = 1.5 v 45 50.9 55 % jitter, absolute 1 t cycle v t = 1.5 v 436 600 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - ref t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -14 ma 2.4 2.6 v output low voltage v ol5 i ol = 6 ma 0.22 0.4 v output high current i oh5 v oh = 2.0 v -32 -20 ma output low current i ol5 v ol = 0.8 v 16 22 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 2.11 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 2.14 4 ns duty cycle 1 d t5 v t = 1.5 v 45 52.1 55 % jitter, cycle to cycle 1 t jcycle5 v t = 1.5 v -600 848 1000 ps 1 guaranteed by design, not 100% tested in production.
10 ICS9248-195 0375d?02/02/04 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel pii/piii "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 5 ics clock will acknowledge each byte one at a time . controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends first byte (byte 0) through byte 5 controller (host) will need to acknowledge each byte controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) ac k byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ac k dummy command code ac k dummy byte count ac k byte 0 ac k byte 1 ac k byte 2 ack byte 3 ac k byte 4 ac k byte 5 ac k stop bit how to write:
11 ICS9248-195 0375d?02/02/04 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
12 ICS9248-195 0375d?02/02/04 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. internal clocks are not running after the device is put in power down. when pd# is active low all clocks need to be driven to a low value and held prior to turning off the vcos and crystal. the power up latency needs to be less than 4 ms. the power down latency should be as short as possible but conforming to the sequence requirements shown below. pci_stop# and clk_stop# are considered to be don't cares during the power down operations. the ref and 48mhz clocks are expected to be stopped in the low state as soon as possible. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248 device). 2. as shown, the outputs stop low on the next falling edge after pd# goes low. 3. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside this part. 4. the shaded sections on the vco and the crystal signals indicate an active clock. 5. diagrams shown with respect to 133mhz. similar operation when cpu is 100mhz. cpuclk pciclk vco crystal pd#
13 ICS9248-195 0375d?02/02/04 clk_stop# timing diagram clk_stop# is an asychronous input to the clock synthesizer. it is used to turn off the cpu clocks for low power operation. clk_stop# is synchronized by the ICS9248-195 . the minimum that the cpu clock is enabled (clk_stop# high pulse) is 100 cpu clocks. all other clocks will continue to run while the cpu clocks are disabled. the cpu clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpu clock on latency is less than 4 cpu clocks and cpu clock off latency is less than 4 cpu clocks. notes: 1. all timing is referenced to the internal cpu clock. 2. clk_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpu clocks inside the ICS9248-195. 3. sdram-f output is controlled by buffer in signal, not affected by the ICS9248-195 clk_stop# signal. sdram are controlled as shown. 4. all other clocks continue to run undisturbed. pciclk sdram cpuclk cpuclk _f sdram_f pci_stop# (high) clk_stop# internal cpuclk
14 ICS9248-195 0375d?02/02/04 pci_stop# timing diagram pci_stop# is an asynchronous input to the ICS9248-195 . it is used to turn off the pciclk clocks for low power operation. pci_stop# is synchronized by the ICS9248-195 internally. the minimum that the pciclk clocks are enabled (pci_stop# high pulse) is at least 10 pciclk clocks. pciclk clocks are stopped in a low state and started with a full high pulse width guaranteed. pciclk clock on latency cycles are only three rising pciclk clocks, off latency is one pciclk clock. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9248. 3. all other clocks continue to run undisturbed. 4. clk_stop# is shown in a high (true) state. cpuclk (internal) pciclk_f (internal) pciclk_f (free-running) clk_stop# pciclk pci_stop#
15 ICS9248-195 0375d?02/02/04 ordering information ics9248 y f-195lf-t index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n designation for tape and reel packaging lead free (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y f lf- t
16 ICS9248-195 0375d?02/02/04 index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c ordering information ics9248 y g-195lf-t 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (0.020 mil) min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 48 12.40 12.60 .488 .496 10-0039 n d mm. d (inch) ref er ence d o c.: jedec pub licat io n 9 5, m o- 153 0.50 basic 0.020 basic see variations see variations see variations see variations 8.10 basic 0.319 basic symbol in millimeters in inches common dimensions common dimensions example: designation for tape and reel packaging lead free (optional) package type g = tssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y g lf- t

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